AccelerComm, the company supercharging 5G with Optimisation and Latency Reduction IP, today announced the availability of its Channel Coding software using the Zynq® UltraScale+™ RFSoC devices from Xilinx, Inc.
AccelerComm also today unveiled a reference kit designed to reduce time to market for 5G NR-compliant FPGA-based solutions by providing a software interface based on the BBDEV api from the Data Plane Development Kit (DPDK) organisation. The kit includes full 3GPP-compliant chain with SD-FEC, DMA, PCIe Interface and glue logic.
The reference board uses the Zynq UltraScale+ ZU21DR from Xilinx which enables designers to jumpstart their RFSoC-based applications. AccelerComm enables deployment of SD FEC resulting in low power consumption and high throughput per watt LDPC. This configurable solution combined with a standard interface offers a range of options allowing specific implementations to be tailored to requirements such as throughput or power constraints – for example when targeting telco cloud edge data centers that are often thermal limited due to physical site size restrictions.
Channel coding, also known as forward error correction, is used to correct transmission errors in mobile communications caused by noise, interference and poor signal strength. This announcement reflects a dramatic change in the direction of channel coding in mobile communications standards. While 3G and 4G used Convolutional and Turbo codes for the control and data channels, 5G uses the much more sophisticated Polar and LDPC codes and requires the industry to look afresh at how to address error correction. If channel coding and the software stack associated is not well constructed the impact on mobile networks is poor capacity, poor data rates, poor coverage and poor quality of service. AccelerComm’s LDPC IP brings many years of experience in forward error correction to address this challenge in the 5G networks now being launched.
“For high data rate applications such as 5G, transmission reliability is a key success factor in the quality of the overall system, making a high-performance SD-FEC a major building block in enabling these systems to function under non-ideal environments,” said Dan Mansur, vice president of marketing, Wired & Wireless Group, Xilinx. “AccelerComm’s channel coding IP is an important addition to the Zynq UltraScale+ RFSoC portfolio. This collaboration will help network equipment manufacturers get to market faster and deliver all-important latency and power consumption improvements in 5G networks.”
“As 5G networks are increasingly rolled out around the globe, we’re seeing greater awareness of the significant challenges that still remain when it comes to latency and power consumption – both of which impact consumer experience and the underlying 5G business case,” said Tom Cronk, CEO of AccelerComm. “This collaboration with Xilinx is a significant endorsement of our ground-breaking channel coding innovations and of the extensive R&D work done over many years by our team.”
AccelerComm’s LDPC IP is fully compliant with the 3GPP NR standard for PDSCH, PUSCH and also supports the full range of uncoded and encoded block sizes. It implements the entire LDPC encoding and decoding chain in 3GPP TS38.212 with superior error correction performance and hardware efficiency. It also tightly integrates the components in the chain to reduce hardware usage and latency and boasts a simple interface, making it quick to integrate.